CPLD - One-Time-Programmable Logic Device - 48 Macrocells
Program Memory Type: EPROM
Number of Global Clocks: 2
Number of Macro Cells: 48
Product Terms: 8
Device System Gates: 900
Data Gate: No
Maximum Number of User I/Os: 64
In-System Programmability: No
Programmability: Yes
Reprogrammability Support: Yes
Maximum Internal Frequency (MHz): 41.67
Maximum Clock to Output Delay (ns): 20
Maximum Propagation Delay Time (ns): 35
Speed Grade: 35
Individual Output Enable Control: No
Minimum Operating Supply Voltage (V): 4.75
Maximum Operating Supply Voltage (V): 5.25
Typical Operating Supply Voltage (V): 5
Minimum Operating Temperature (°C): 0
Maximum Operating Temperature (°C): 70
EP1810.pdf
