EE CMOS High Performance Programmable Array Logic
- Electrically-erasable CMOS technology
- Sixteen macrocells with configurable I/O architecture
- Registered or combinatorial operation
- Registers programmable as D, T, J-K, or S-R
- Asynchronous clocking via product term or bank register clocking from external pins
- Register preload for testability
- Power-up reset for initialization
- Supply Voltage (VCC): +4.75 V to +5.25 V
- Ambient Temperature (TA): 0°C to +75°C
Datenblatt:
PALCE610H-25PC.pdf
