Programmable Logic Device ACEX 1K Family
- Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array block (EAB)
– Logic array for general logic functions
- High density
– 10,000 to 100,000 typical gates
– Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity
- Cost-efficient programmable architecture for high-volume applications
– Cost-optimized process
– Low cost solution for high-performance communications applications
- System-level features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
– Low power consumption
– Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz
– Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
data sheet:
EP1K100QC208-3N.pdf
