DRAM Chip SDR SDRAM 128M-Bit 4Mx32 3.3V
- PC100 functionality
- Fully synchronous; all signals registered on positive edge of system clock
- Internal pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Programmable burst lengths: 1, 2, 4, 8, or full page
- Auto precharge, includes concurrent auto precharge, and auto refresh modes
- Self refresh mode (not available on AT devices)
- Auto refresh: 64ms, 4,096-cycle refresh (15.6?s/row) (commercial & industrial)
– 16ms, 4,096-cycle refresh (3.9?s/row) (automotive)
- LVTTL-compatible inputs and outputs
- Single +3.3V ±0.3V power supply
- Supports CAS latency (CL) of 1, 2, and 3
data sheet:
MT48LC4M32B2.pdf
