384 macrocell CPLD
- Low power 3.3V 384 macrocell CPLD
- 7.0 ns pin-to-pin logic delays
- System frequencies up to 135 MHz
- 384 macrocells with 9,000 usable gates
- Optimized for 3.3V systems
- Ultra low power operation
- Typical Standby Current of 18 ?A at 25° C
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM process
- Fast Zero Power™ (FZP) CMOS design technology
- 3.3V PCI electrical specification compatible outputs
data sheet:
XCR3384XL.pdf
