16bit General Purpose Digital Signal Processor
— Up to 30 Million Instructions Per Second (MIPS) – 33 ns instruction cycle at 60 MHz
— Up to 180 Million Operations Per Second (MOPS) at 60 MHz
— Highly parallel instruction set with unique DSP addressing modes
— Two 40-bit accumulators including extension byte
— Parallel 16 ´ 16-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
— Double precision 32 ´ 32-bit multiply with 72-bit result in 6 instruction cycles
— Least Mean Square (LMS) adaptive loop filter in 2 instructions
— 40-bit Addition/Subtraction in 1 instruction cycle
— Fractional and integer arithmetic with support for multiprecision arithmetic
— Hardware support for block-floating point FFT
— Hardware-nested DO loops including infinite loops
— Zero-overhead fast interrupts (2 instruction cycles)
— Three 16-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip
data sheet:
XC56156.pdf
