Spartan-IIE FPGA Family
- Densities as high as 15,552 logic cells with up to 600,000 system gates
- Streamlined features based on Virtex®-E FPGA architecture
- Unlimited in-system reprogrammability
- Very low cost
- Cost-effective 0.15 micron technology
- Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant
- Low-power segmented routing architecture
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Eliminate clock distribution delay
- Multiply, divide, or phase shift
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
data sheet:
XC2S400E.pdf
